Xilinx (pronounced “zye-links”) is one of those funny-named, specialized companies that makes a cog in data center machinery that is important for efficiency’s sake but that is so melded into the infrastructure that it’s easy to be overlooked.
The San Jose, Calif.-based chipmaker, which makes an item called a field-programmable gate array, or FPGA for short, on March 19 announced a new product that it says will eventually supercede what its frontline product already does in an IT system.
It’s called an adaptive compute acceleration platform (ACAP), and Xilinx claims this proprietary 7nm chip goes far beyond the capabilities of an FPGA, which are already in wide use. It’s still vaporware at this point, however, with testing beginning later this year.
Setting a Context for the Changeover
To set context, let’s define FPGAs first: These are a group of accelerators used to help speed up the performance of large-scale systems while keeping a lid on power consumption. Accelerators—particularly GPUs from Nvidia and Advanced Micro Devices and x86 Xeon Phi co-processors from Intel—have been used in high-performance computing (HPC) and supercomputing environments. However, with the growth in the number of connected devices and the accompanying data, the rise of cloud computing and the internet of things (IoT), and the increasing amount of video in network traffic, the use of accelerators is expanding.
Intel officials have said they expect FPGAs to be used in as many as 30 percent of all data center servers by 2020. Xilinx and Altera have been the primary vendors behind the development of FPGAs, which have the added benefit of being able to be reprogrammed for different workloads.
But here’s what an ACAP brings to the table, according to Xilinx: This is a highly integrated, multi-core chip that can be changed out without penalty to the workload to adapt to the needs of a wide range of applications and workloads. An ACAP’s adaptability, which the company said can be managed during operation and ostensibly not impact production, delivers levels of performance and performance per-watt above that offered by current CPUs or GPUs, Xilinx said.
Accelerates Multiple Applications at Once
An ACAP is suited to accelerate a large set of applications in the emerging era of big data and artificial intelligence, Xilinx said. These include video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for endpoint and cloud applications.
The first ACAP product line, codenamed Everest, has been under development for four years at an accumulated R&D investment of more than $1 billion, Xilinx said. There are currently more than 1,500 hardware and software engineers at Xilinx designing the new chips. Software tools to implement them have been delivered to key customers. Everest will enter testing later this year with customer shipments expected in 2019.
“This is a major technology disruption for the industry and our most significant engineering accomplishment since the invention of the FPGA,” CEO and President Victor Peng said in a media advisory. “This revolutionary new architecture is part of a broader strategy that moves the company beyond FPGAs and supporting only hardware developers.
“The adoption of ACAP products in the data center, as well as in our broad markets, will accelerate the pervasive use of adaptive computing, making the intelligent, connected and adaptable world a reality sooner.”
Techical Information about Everest
An ACAP has a lot of things in it. It is new-generation FPGA fabric processor with distributed memory and hardware-programmable DSP blocks, a multicore SoC (system on a chip), and one or more software programmable, yet hardware adaptable, compute engines--all connected through a network on chip (NoC). An ACAP also has highly integrated programmable I/O functionality, ranging from hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated high bandwidth memory (HBM), depending on the device variant.
Software developers will be able to target ACAP-based systems using standard tools that include C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.
“This is what the future of computing looks like,” analyst Patrick Moorhead, founder of Moor Insights & Strategy, said in a media advisory. “We are talking about the ability to do genomic sequencing in a matter of a couple of minutes, versus a couple of days. We are talking about data centers being able to program their servers to change workloads depending upon compute demands, like video transcoding during the day and then image recognition at night. This is significant.”
Everest is expected to achieve 20x performance improvement on deep neural networks compared to the latest 16nm Virtex VU9P FPGA. dwsEverest-based 5G remote radio heads will have 4x the bandwidth versus the latest 16nm-based radios, Xilinx said. A variety of applications across multiple markets such as automotive; industrial, scientific and medical; aerospace and defense; test, measurement and emulation; audio/video and broadcast; and the consumer markets are expected to see a significant performance increase and greater power efficiency.
ACAP and the Everest project are a major part of Peng’s vision for the future of Xilinx. Xilinx’s new strategy involves three key points:
- New emphasis on data center acceleration: Xilinx is ramping up its efforts with key data center customers, ecosystem partners and software application developers, to further enable innovation and deployments in compute acceleration, computational storage and network acceleration.
- Accelerating growth in core markets: These markets include automotive; wireless infrastructure; wired communications; audio, video and broadcast; aerospace and defense; industrial, scientific and medical; test, measurement and emulation; and consumer technologies. These core markets and customers remain central to Xilinx.
- Introducing the Adaptive Compute Acceleration Platform (ACAP): The third pillar is the announcement of the new product.
“While FPGA and Zynq SoC technologies are still core to our business, Xilinx is not just an FPGA company anymore,” Peng said. “That is our heritage, but we have been building upon that foundation for years now: integrating full SoCs onto our programmable dies, developing 3D ICs, building out software development frameworks and creating partner ecosystems to deliver products that are completely unique to the industry.
“We are taking this innovation to the next level with the invention of the ACAP.”
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